TPX4004 Carrier Packet Engine
The TPX4004 Carrier Packet Engine is designed for use in Carrier Ethernet and Packet Transport applications.
Product Documentation for TPX4004:
The key features of the TPX4004 are:
- 40-80 Gbps full duplex non-blocking L2 switch
- Fully deterministic packet processing performance at wire speed
- Includes advanced, programmable hierarchical traffic scheduler and shaper
- Flexible support for interworking with various switch fabrics
- True MEF-defined Carrier Class support with large packet buffer and L2-address space
- Extensive hardware based Ethernet and MPLS OAM support
- Multi-protocol support for Ethernet Q-in-Q, PBB, PBB-TE, MPLS, T-MPLS, and MPLS-TP
Focusing on Carrier Ethernet and MPLS support at Layer 2/2.5, the TPX4004 addresses the emerging need for packet intelligence in Transport Networks. In this regard, it includes a number of features not typically included in Enterprise Ethernet switches or router packet processor chips. For example, the TPX4004 includes support for all major metro protocols including PBB-TE, PBB, VPLS and the emerging MPLS-TP. It also includes hardware based OAM support for these protocols with extremely fast OAM transmission/reception (3.3ms period) allowing sub-50ms hardware-based Automatic Protection Switching. TPX4004 also includes configurable support for 9 layers of hierarchical traffic management.
In order to support the various system architecture approaches being adopted, the TPX4004 allows traffic management and virtual output queuing to be added and removed depending on the needs of the packet fabric switches incorporated in the system design. This allows the TPX4004 to fit into almost any switch architecture or design.
The TPX4004 is delivered as a SOFTSILICON product including:
- Altera Stratix IVGX 40nm device
- FPGA image software implementing TPX4004 features and interfaces
- Associated driver software
See also:
TPX3103 52 Gbps Carrier Packet Engine
TPX3100 40 Gbps Carrier Packet Engine
TPX2000 6 Gbps Carrier Packet Engine