Soft Solutions for hard TEM times

As telecom equipment manufacturers struggle to improve financial performance and make sense out of alternative solutions for packet transport, new ‘soft solutions’ offer flexibility, and faster time-to-market, which could provide the key to their future success.

By DANIEL JOSEPH BARRY
TPACK

As the telecom industry transitions to a full packet-based, converged world, alternative technologies are battling for position in various segments of the network. Packet transport and switching is a major battleground as telecom equipment manufacturers (TEMs) examine a confusing array of solutions.

For carrier Ethernet services transport alone, there are multiple technology choices that include synchronous optical network/synchronous digital hierarchy (SONET/SDH), multi-protocol label switching (MPLS), provider backbone transport (PBT), transport-MPLS (TMPLS), virtual private LAN service (VPLS), and pseudo-wire emulation edge-to-edge (PWE3), to name a few. Ongoing development and standardization of these technologies only add to the confusion.

Success in packet transport, and carrier Ethernet in particular, is essential for both carriers and TEMs, as these provide the cost-effective infrastructure for future converged packet-based services. Navigating the confusion and finding a strategy to support the wide array of alternatives presents a major challenge.

The key to success for TEMs is to focus on efficiency throughout their system development process while maintaining the ability to quickly react to market changes and new customer requirements. This is achievable by re-assessing the way systems are built, deployed and upgraded. This article will introduce two new system-level and chip-level solutions – SOFTSILICON and SOFTSYSTEM – that will help TEMs manage the challenging transition from circuit to packet transport.

SOFTSILICON is a standard, off-the-shelf chip solution based on a re-programmable platform, namely a Field Programmable Gate Array (FPGA). This allows the comprehensive standard feature set to be adapted and extended for accommodating proprietary requirements, extra features or new standards – even after deployment. Adding application and management software in an integrated package provides a SOFTSYSTEM solution, ready for integration into existing or new TEM platforms.

Basing a system development approach on SOFTSILICON and SOFTSYSTEM provides TEMs with the flexibility and speed necessary to survive in the current confusing packet transport environment without compromising cost or increasing risk.

TEMs under pressure

While many telecom carriers have improved net income over the past five years, it has been at considerable cost to TEMs. The increased demands of carriers have put the squeeze on net income and profits for TEMs, in many cases to single digit or even negative margins. Since there is no expected upswing in carrier spending, TEMs must make every effort to win market share in key carrier investment areas while improving margins through the efficient use of resources.

Carrier margin pressure creates a “trickle down” effect that is being felt all the way down to the system component supplier levels, basically the semiconductor companies. Packet transport solutions require fewer semiconductor chips. This lowers the volume demand which is even further split between competing technologies and protocols to create higher cost and insufficient supplies. Semiconductor chip companies simply cannot justify investment in new packet transport chip applications. This leaves TEMs either settling for existing solutions or developing solutions in-house, further undermining their own cost performance.

With the increase in alternative solutions to the same packet transport conundrum, settling for existing solutions is not an option for TEMs; new options need to be supported that ensure no customers are left un-addressed. The key issue is how to support all of these options and keep up with regular standard updates, while keeping time-to-market and cost in check.

Competitive strategy

In short, if a TEM expects to remain competitive in today’s turbulent market, it should adopt a system development strategy that promises flexibility, rapid time-to-market, reduced risk, and lower cost.

In terms of flexibility, the strategy must be agile – able to quickly add, modify and adapt system features to market and customer feedback. The capability must exist to rapidly switch to the dominant market design if it isn’t currently supported, or support more than one approach. Accommodations must also be made to allow for differentiating features and legacy support.

For faster time-to-market, the solution must enable quick introduction of a system implementation while supporting continuous upgrades that are focused on improving key performance criteria. Implementation risk must be minimized to maintain lower overall development and support costs. TEMs must also ensure that development cost and target cost per unit can continually be reduced.

The key is making changes and improvements through the underlying chip technology that supports system development. By introducing flexibility into chip implementations, TEMs can adapt both software and hardware to customer and market needs – resulting in increased market share and competitiveness.

A comparison of various chip technologies with respect to flexibility, time-to-market, and cost is shown in Table 1. Clearly, while ASIC and ASSP approaches deliver cost benefits, it’s at the cost of either time-to-market or flexibility. However, new strides in programmable chip technology, such as FPGAs, enable all three goals to be achieved. Compared to Network Processing Units (NPUs), FPGAs add additional flexibility by enabling all of the functions (not just packet processing) and interfaces to be defined using software. A repeatable programming process makes FPGAs ideal for accommodating adaptations, customizations, and upgrades.

With stretched resources that must both master new chip technologies while remaining competent in legacy technologies, TEMs are facing tough decisions regarding their ability for in-house chip development. What is now required is an ASSP-like solution that can still meet the market’s increasing flexibility demands. The answer is a ‘soft’ solution.

The ‘soft’ advantage

SOFTSILICON and SOFTSYSTEM are two inter-related concepts for the development of standard, software-based solutions. These soft solutions offer built-in flexibility that enables TEMs to achieve systems that can be quickly adapted to meet customer and market needs without sacrificing time-to-market or cost.

First, the SOFTSILICON solution combines a standard, off-the-shelf programmable chip – specifically an FPGA – with a software image that programs the FPGA to provide a set of hardware functions and interfaces. FPGAs enable the use of standard feature sets and supporting interfaces that can rapidly be modified. This, in turn, allows faster development and deployment, as well as easier adaptation to unforeseen market requirements.

While FPGAs typically allow TEMs to develop their own solutions, SOFTSILICON is a standard chip solution that is provided by a specialist vendor, similar to ASSPs. The vast majority of the chip features will not require adaptation. However, TEMs may still need adaptations and customizations to accommodate proprietary interfaces, functions or a legacy solution. SOFTSILICON provides the best of both worlds – a finished standard product that, if necessary, can still save time and resources by accommodating different features and adaptations.

A SOFTSILICON solution is provided with integrated high-level driver API software that implements a high-level abstraction of the features provided by the chip. This enables easy integration of application and management software. The result is a flexible, standard solution that can be implemented and adapted quickly to TEMs’ system solutions.

While understanding what a SOFTSILICON solution is, it is also important to know what it is not. SOFTSILICON is not an intellectual property block for integrating into an existing TEM FPGA design. It is an optimized design with an architecture focused on efficient use of available FPGA resources. SOFTSILICON is delivered as an FPGA image intended for a single FPGA device with adaptations and extensions performed by the SOFTSILICON vendor – and it is also the basis for a SOFTSYSTEM.

A SOFTSYSTEM is the result of developing SOFTSILICON chip solutions with a system focus from the beginning. This system would include a SOFTSILICON chip solution, chip control software, reference application software, reference management software, and ongoing support and maintenance.

The SOFTSYSTEM development approach based on SOFTSILICON combines the cost and time-to-market advantages of ASSPs with the flexibility of FPGAs while providing a reference solution that helps reduce implementation risk. This approach also provides longer lifetime benefits since field upgrades and the reuse of software are now possible.

Conclusion

In a market where the only certain thing is change, TEMs must rethink their system development processes. As carriers push harder and harder for a wider breadth of solution support and key technology suppliers bounce from application to application to force more in-house development, remaining competitive is becoming a greater challenge for TEMs.

A SOFTSYSTEM approach based on commercial SOFTSILICON chips helps TEMs meet that challenge by accelerating time-to-market and reducing development costs. The added bonus is basing these chips on programmable FPGAs that allow the flexibility necessary to adapt to customized requirements. Through the implementation of SOFTSILICON, TEMs can not only deal with the challenges they face today, but also remain agile enough to respond to new market opportunities quickly. A soft approach to a telecom market facing uncertainty makes flexibility a key component for being competitive. 

Daniel Joseph Barry is the director of marketing for TPACK (www.tpack.com), headquartered in Herlev, Denmark.