TPACK provides smart solutions based on smart people with deep experience and a unique combination of skills. Find out more about why TPACK is different.

TPACK has been fortunate to gather some of the leading engineers in Denmark in the areas of:

• FPGA/ASIC design and programming
• Embedded design for Datacom and Telecom systems
• System design
• Datacom/Packet networks (e.g Ethernet, IP/MPLS)
• Telecommunication networks (e.g. SONET/SDH, PDH)

With 10 to 15 years experience per employee, the TPACK team is one of the most experienced in the business leading to some unique core competencies:

Combined Datacom and Telecom Experience

Finding engineers with experience of traditional telecommunication networks and standards, such as SONET/SDH and PDH, as well as a thorough understanding of packet networks, such as Ethernet, MPLS and IP, can be very difficult. TPACK's engineers have typically worked at several companies in both fields including telecom companies, such as Tellabs, Ericsson, Alcatel, ADC, TDC, Telia as well as datacom companies such as Cisco, Dataco/Case Communications and Olicom.

By understanding the needs of telecom carriers and vendors and combining this with a deep knowledge of packet networks, TPACK is in a unique position to create solutions with ease the migration of telecom networks from traditional circuit to packet-based technology.

Faster, Right First Time Solutions

Based on this experience, TPACK can develop and provide products and solutions quicker and with a higher level of quality than most other vendors. By engaging with TPACK, several customers have shortened development lifecycles, decreased Time-to-Market and reduced the number of errors and board re-spins during development and bring-up.

More functionality, in less space

TPACK FPGA/ASIC design engineers have used their considerable experience from companies such as MIPS, Intel, LSI Logic, PMC Sierra, Galazar, Transwitch and Vitesse to provide ground-breaking FPGA-based chip solutions. TPACK excels in providing more functionality per logic unit than other vendor. TPACK designs can typically use less than half the number of logic elements seen in other FPGA designs or IP blocks. This allows TPACK to provide seemingly impossible solutions, such as a full 10Gbps Ethernet over SONET/SDH packet mapper with Low Order support in a single chip or a combined 40Gbps packet processor and traffic manager.